Today, it's not an overstatement to say that programmable logic is at the foundation of SoC design verification. The ability to run a design at hundreds of kHz to hundreds of MHz -- as opposed to dozens of clock ticks per second for software simulation -- opens whole new strategies for functional verification. And the emotional impact of having a real, nonsoftware implementation on the desk in front of you, while maybe not entirely rational, is nonetheless tangible.

A spectrum of solutions
Ran Avinun,director of marketing for vertical solutions at QuickTurn, suggests that you can line FPGA-based verification approaches up to create a spectrum of alternatives. At one end you would have roll-your-own approaches, in which the design team simply designs an FPGA-based version of the ASIC. Further up the spectrum, there is a small cluster of vendors providing prototyping boards with one, or sometimes a few, FPGAs on them, intended for easy configurability and interfacing.In some cases those boards come from design ervices providers like the Dini Group. Further yet,and you get into purpose-built, rapid-prototyping systems. Those products bundle a board or chassis,often capable of handling quite a number of FPGAs,with configurable interconnect, synthesis and analysis software. Finally, at the far end of the line would be the ''big iron'' ASIC emulations systems.

Each point on that spectrum has its inhabitants and its particular uses. In fact, a single design may employ techniques from several different points along the line for different purposes.

Surprisingly, a number of seemingly unrelated variables change monotonically as you move along the line. An obvious example is cost: a roll-your-own FPGA board can be as inexpensive as an evaluation chip you happened to have in the desk, plus a one-off pc board. Even a whole pilot run of FPGA prototypes can provide co-development platforms to get the software team going without incurring the expense of a midrange,rapid-prototyping system. The latter systems range around $50,000 -- for a limited system intended for software co-design -- up to a few hundred thousand dollars for a fairly intense, multi-FPGA hardware verification platform. The big iron can really get up there, in some estimates costing between 50 cents and a dollar per emulated gate.

The level of visibility changes as you go along the continuum as well. If you roll your own board, the signals you get to see have,until recently, been the signals you chose to bring out to pins. Rapid-prototyping solutions typically provide more visibility, but at selected levels of abstraction. Some only give easy access to the boundaries between blocks. Others give best visibility at the RT level rather than node level. The emulation systems come into their own on this parameter, giving the same level of visibility, and often the same look and feel,as mainstream software simulation environments.

This picture is changing rapidly, however, as the FPGA vendors recognize the importance of verification to their customers. David Greenfield, director of development tools marketing at Altera Corp., pointed out that the introduction of SignalTap -- in essence an internal logic analyzer with access to every node in the FPGA -- had enormously improved the hardware verification capabilities of recent Altera parts. Nor is the capability unique to Altera. The new capabilities are cutting into the need for third-party verification systems, Greenfield believes, but are primarily for designs that will fit into a single giant FPGA.

Partitioning is another issue that changes along the continuum.Roll your own, and the problems of partitioning your ASIC design across multiple FPGAs are pretty much yours. Prototyping systems generally excel at handling this problem transparently, at least at a particular level of abstraction. Emulation systems, which can often double as simulation accelerators, make the boundary between FPGAs invisible. Some designers say that partitioning is the key parameter in choosing an emulation approach. If your design partitions comfortably in six or fewer FPGAs, a roll-your-own board may be the most practical. If it takes more chips than that, the FPGA-based, roll-your-own design may be at least as complicated as the ASIC you are trying to verify.

Speed is yet another such variable. But unlike almost everything else, the more you pay the slower you go. Roll-your-own systems usually run at the maximum frequency you care to wring out of the FPGAs. QuickTurn's Avinun points out that in the communications space, many FPGA prototypes can run fast enough to handle OC-192 data, and so can be shipped to early customers as is.

Rapid-prototyping systems insert more debug structures into the design and often partition the design among multiple FPGAs, reducing operating speeds. Lee Todd, senior director of business development at Simutech, suggests ''we tell customers to expect between 1 and 5 MHz for signals that cross our backplane.'' The big-iron systems typically emulate at effective clock frequencies in the low to moderate thousands per second -- still much greater speed than software simulation,but with all the observability and controllability of the software tools.

Finally, the nature of the abstraction changes as you move along the line. In roll-your-own designs, a logic cell in the FPGA implements a piece of your RTL design. The mapping is virtually one to one, although it can be challenging to track an anomalous node result back to the RTL source. Rapid-prototyping systems typically combine your design with additional code for observability, controllability and partitioning, so that the logic cell maps of the FPGAs would mean very little to you. But the vendors provide their own verification software to interface you to the model they created.

The big systems carry this to the extreme of making every node alterable and observable on every clock cycle. But vendors use several very different techniques to accomplish this. Some, Ikos for example, use off-the-shelf,recent-model FPGAs to implement a blend of your design and their instrumentation. They pay a price for this in compile time, according to Ikos senior director of product marketing Mitch Dale, but there is one enormous advantage: Ikos'performance advances along with Xilinx's product development curve.

A variant of that approach is used by QuickTurn's Mercury family. The company developed their own fine-grained FPGA, giving very fast compile times and good simulation speed.

In contrast, QuickTurn's Cobalt and Paladium families are based not on programmable logic, but on arrays of evaluation processors. In effect, they are simulation accelerators that are configured to the design during the compilation process. The result is slower execution, but more flexibility.

A hybrid approach comes from a smaller vendor using reconfigurable computing techniques. Axis Systems does both simulation acceleration and ASIC emulation by configuring off-the-shelf FPGAs to be custom processors. The company has a library of custom processors that it configures into the FPGA array based on its analysis of the behavioral or RTL design source, and then the processors perform an event-based simulation. Virtually all other prototyping and emulation systems are cycle-driven.

So there is a range of approaches. Based on needs, inclinations and budget, you get to take your choice. Based on the growing acceptance of these tools among design teams, the value is there.